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slvs179d ? march 1999 ? revised june 2000 1 post office box 655303 ? dallas, texas 75265 fully integrated xvcc and xvpp switching xvpp programmed independent of xvcc 3.3-v, 5-v, and/or 12-v power distribution low r ds(on) (60-m ? xvcc switch typical) short circuit and thermal protection 150- a (maximum) quiescent current standby mode: 50-ma current limit (typ) 12-v supply can be disabled 3.3-v low-voltage mode meets pc card ? standards ttl-logic compatible inputs available in 30-pin ssop (db) and 32-pin tssop (dap) packages break-before-make switching internal power-on reset description the tps2216 pc card power-interface switch provides an integrated power-management solution for two pc cards. all of the discrete power mosfets, a logic section, current limiting, and thermal protection for pc card control are combined on a single integrated circuit. this device allows the distribution of 3.3-v, 5-v, and/ or 12-v power to the card. the current-limiting feature eliminates the need for fuses. current- limit reporting can help the user isolate a system fault. the tps2216 features a 3.3-v low-voltage mode that allows for 3.3-v switching without the need for 5-v power. this feature facilitates low-power system designs such as sleep modes where only 3.3 v is available. this device also has the ability to program the xvpp outputs independent of the xvcc outputs. a standby mode that changes all output-current limits to 50 ma (typical) has been incorporated. end-equipment applications for the tps2216 include: notebook computers, desktop computers, personal digital assistants (pdas), digital cameras, and bar-code scanners. the tps2216 is backward-compatible with the tps2202a and tps2206. copyright ? 2000, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. pc card is a trademark of pcmcia (personal computer memory card international association). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5v 5v nc data clock latch reset 12v avpp avcc avcc avcc gnd reset nc 3.3v 5v nc mode nc nc nc nc 12v bvpp bvcc bvcc bvcc oc stby 3.3v 3.3v dap package ? (top view) nc ? no internal connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5v 5v data clock latch reset 12v avpp avcc avcc avcc gnd nc reset 3.3v 5v mode nc nc nc nc 12v bvpp bvcc bvcc bvcc stby oc 3.3v 3.3v db package ? (top view) ? the tps2216 is identical to the tps2214 in all respects except packaging and pin assignments.
slvs179d ? march 1999 ? revised june 2000 2 post office box 655303 ? dallas, texas 75265 available options packaged devices ? t j plastic small outline (db) powerpad plastic small outline ? (dap) ?40 c to 125 c tps2216db(r) TPS2216DAP(r) ? the db and dap packages are available in tubes and left-end taped and reeled. add r suffix to device type (e.g., tps2216dbr) for taped and reeled. terminal functions terminal name no. i/o description name db dap i/o description 3.3v 15, 16, 17 16, 17, 18 i 3.3-v input for card power and/or chip power if 5 v is not present 5v 1, 2, 30 1, 2, 32 i 5-v input for card power and/or chip power 12v 7, 24 8, 25 i 12-v v pp input card power avcc 9, 10, 11 10, 11, 12 o vcc output: 3.3-v, 5-v, gnd or high impedance to card avpp 8 9 o vpp output: 3.3-v, 5-v, 12-v, gnd or high impedance to card bvcc 20, 21, 22 21, 22, 23 o vcc output: 3.3-v, 5-v, gnd or high impedance to card bvpp 23 24 o vpp output: 3.3-v, 5-v, 12-v, gnd or high impedance to card gnd 12 13 ground mode 29 30 i tps2206 operation when floating or pulled low; must be pulled high externally for tps2216 operation. mode is internally pulled low with a 150-k ? pulldown resistor. oc 18 20 o logic-level output that goes low when an overcurrent or overtemperature condition exists. reset 6 7 i logic-level reset input active high. do not connect if reset pin is used. reset is internally pulled low with a 150-k ? pulldown resistor. reset 14 14 i logic-level reset input active low. do not connect if reset pin is used. the pin is internally pulled high with a 150-k ? pullup resistor. stby 19 19 i logic-level active low input sets the tps2216 to standby mode and sets all current limits to 50 ma. the pin is internally pulled high with a 150-k ? pullup resistor. clock 4 5 i logic-level clock for serial data word data 3 4 i logic-level serial data word latch 5 6 i logic-level latch for serial data word nc 13, 25, 26, 27, 28 3, 15, 26, 27, 28, 29, 31 no internal connection powerpad is a trademark of texas instruments incorporated.
slvs179d ? march 1999 ? revised june 2000 3 post office box 655303 ? dallas, texas 75265 functional block diagram (pin numbers refer to db package) ? both 12v pins must be connected together. tps2216 avcc 3.3v 15 12v ? 12v ? 5v 5v 5v 3.3v 3.3v bvpp bvcc bvcc bvcc avpp avcc avcc 16 29 24 7 30 2 1 17 6 5 4 3 19 18 14 9 10 11 8 20 21 22 23 s7 s8 s9 s10 cs cs cs s11 s12 s13 s14 cs cs cs s2 cs cs s3 s5 cs cs s6 s4 mode reset latch clock data stby oc reset internal current monitor thermal gnd 12 s1
slvs179d ? march 1999 ? revised june 2000 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating virtual free-air temperature (unless otherwise noted) ? input voltage range for card power: v i(3.3v) ?0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v i(5v) ?0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v i(12v) ?0.3 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic input voltage ?0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range: v o(xvcc) ?0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v o(xvpp) ?0.3 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current: i o(xvcc) internally limited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i o(xvpp) internally limited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating virtual junction temperature range, t j ?40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. dissipation rating table package t a 25 c power rating derating factor ? above t a = 25 c t a = 70 c power rating t a = 85 c power rating db 1095 mw 10.99 mw/ c 602 mw 438 mw dap 4255 mw 42.55 mw/ c 2340 mw 1702 mw ? these devices are mounted on an jedec low-k board (2 oz. traces on surface), 1-w power applied. recommended operating conditions min max unit v i(3.3v) 2.7 5.25 v input voltage, v i v i(5v) 2.7 5.25 v input voltage, v i v i(12v) 2.7 13.5 v output current, i o i o(vcc) at t a = 70 c 1 a output current, i o i o(vpp) at t a = 70 c 200 ma clock frequency 2.5 mhz data 200 pulse duration latch 250 ns pulse duration clock 100 ns data hold time 100 ns data setup time 100 ns latch delay time 100 ns clock delay time 250 ns operating virtual junction temperature, t j ?40 125 c refer to figures 2 and 3.
slvs179d ? march 1999 ? revised june 2000 5 post office box 655303 ? dallas, texas 75265 electrical characteristics, t j = 25 c, v i(5v) = 5 v, v i(3.3v) = 3.3 v, v i(12v) = 12 v, stby floating, all outputs unloaded (unless otherwise noted) power switch parameter test conditions min typ max unit t j = 25 c, i o = 1 a 60 85 3.3 v to xvcc, with one t j = 125 c, i o = 1 a 90 120 3.3 v to xvcc, with one switch on t j = 25 c, v i(5v) = 0, i o = 1 a 65 85 switch on t j = 125 c, v i(5v) = 0, i o = 1 a 90 130 5 v to xvcc, with one t j = 25 c, i o = 1 a 60 85 5 v to xvcc, with one switch on t j = 125 c, i o = 1 a 90 120 m ? c, i o = 1 a each 65 105 m ? 3.3 v to xvcc, with two t j = 125 c, i o = 1 a each 95 140 switch ? 3.3 v to xvcc, with two switches on t j = 25 c, v i(5v) = 0, i o = 1 a each 70 105 switch resistance ? switches on t j = 125 c, v i(5v) = 0, i o = 1 a each 100 140 resistance 5 v to xvcc, with two t j = 25 c, i o = 1 a each 70 105 5 v to xvcc, with two switches on t j = 125 c, i o = 1 a each 100 140 3.3 v/5 v/12 v to xvpp t j = 25 c, i o = 50 ma 0.7 1 3.3 v/5 v/12 v to xvpp t j = 125 c, i o = 50 ma 1.4 2.5 3.3 v/5 v to xvcc t j = 25 c, stby = low, i o = 30 ma 1.4 2 ? c, stby = low, i o = 30 ma 2 3 ? 3.3 v/5 v/12 v to xvpp t j = 25 c, stby = low, i o = 30 ma 5 7 3.3 v/5 v/12 v to xvpp t j = 125 c, stby = low, i o = 30 ma 10 16 clamp low v o(xvcc) i o(xvcc) at 10 ma, after reset 0.275 0.8 v clamp low voltage v o(xvpp) i o(xvpp) at 10 ma, after reset 0.275 0.8 v i o(xvcc) high-impedance t j = 25 c 1 10 i lkg leakage current i o(xvcc) high-impedance state t j = 125 c 2 50 a i lkg leakage current i o(xvpp) high-impedance t j = 25 c 1 10 a i o(xvpp) high-impedance state t j = 125 c 2 50 i o(xvcc) t j = 85 c, output powered into a short to gnd 1 2.2 a i short-circuit output current i o(xvpp) t j = 85 c, output powered into a short to gnd 250 500 ma i os short-circuit output current limit ? standby mode i o(xvcc) t j = 85 c, output powered into a short to gnd, 35 50 65 ma limit ? standby mode i o(xvpp) j output powered into a short to gnd, stby = 0 v 30 50 60 ma current limit ? xvcc switch 100-m ? short circuit 100 s current limit response time ? xvpp switch 100-m ? short circuit 16 s i i(3.3v) 0.01 2 normal operation i i(5v) v o(xvcc) = v o(xvpp) = 5 v 100 120 a normal operation and in reset i i(12v) v o(xvcc) = v o(xvpp) = 5 v 6 10 a and in reset mode i i(3.3v) v i(5v) = 0, v o(xvcc) = 3.3 v, 100 120 i i input current mode i i(5v) v i(5v) = 0, v o(xvcc) = 3.3 v, v o(xvpp) = 12 v 0 a i i input current i i(12v) v o(xvpp) = 12 v 22 30 a i i(3.3v) 1 shutdown mode i i(5v) v o(xvcc) = hi-z, v o(xvpp) = hi-z 1 a shutdown mode i i(12v) v o(xvcc) = hi-z, v o(xvpp) = hi-z 1 a thermal ? trip point, t j 155 c thermal shutdown ? hysteresis 10 c ? pulse-testing techniques maintain junction temperature close to ambient temperature (250- s-wide pulse, less than 0.5% duty cycle); thermal effects must be taken into account separately. ? specified by design, not tested in production. input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inacti ve. note: v i(3.3v) or v i(5v) must be biased for switches to function.
slvs179d ? march 1999 ? revised june 2000 6 post office box 655303 ? dallas, texas 75265 logic section (clock, data, latch, mode, reset, reset , stby , oc ) parameter test conditions min typ max unit i or i ? v i(reset) = 5 v or v i(reset ) = 0 v 30 50 i i(reset) or i i(reset ) ? v i(reset) = 0 v or v i(reset ) = 5 v 1 i i(mode) ? v i(mode) = 5 v 30 50 logic input current i i(mode) ? v i(mode) = 0 v 1 a logic input current i i(stby ) ? v i(stby ) = 5 v 1 a i i(stby ) ? v i(stby ) = 0 v 30 50 i i(clock) or i i(data) or i i(latch) 1 logic input high level v i(5v) = 5 v 2 v logic input high level v i(5v) = 0 v 2 v logic input low level 0.8 v logic output high level, oc v i(5v) = 5 v, i o = 1 ma v i(5v) ?0.4 v logic output high level, oc v i(5v) = 0 v, i o = 1 ma v i(3.3v) ?0.4 v logic output low level, oc i o = 1 ma 0.4 v ? reset and mode have internal 150-k ? pulldown resistors; reset and stby have internal 150-k ? pullup resistors.
slvs179d ? march 1999 ? revised june 2000 7 post office box 655303 ? dallas, texas 75265 switching characteristics parameter ? load condition ? test conditions ? min typ max unit c l(xvcc) = 0.1 f, c l(xvpp) = 0.1 f, v o(xvcc) 1 t r output rise times ? c l(xvpp) = 0.1 f, i o(xvcc) = 0 , i o(xvpp) = 0 v o(xvpp) 0.8 ms t r output rise times ? c l(xvcc) = 150 f, c l(xvpp) = 10 f, v o(xvcc) 1.2 ms c l(xvpp) = 10 f, i o(xvcc) = 1 a, i o(xvpp) = 50 ma v o(xvpp) 2.5 c l(xvcc) = 0.1 f, c l(xvpp) = 0.1 f, v o(xvcc) 0.01 t f output fall times ? c l(xvpp) = 0.1 f, i o(xvcc) = 0 , i o(xvpp) = 0 v o(xvpp) 0.01 ms t f output fall times ? c l(xvcc) = 150 f, c l(xvpp) = 10 f, v o(xvcc) 3 ms c l(xvpp) = 10 f, i o(xvcc) = 1 a, i o(xvpp) = 50 ma v o(xvpp) 8 latch to xvpp (12 v) t pd(on) 3 latch to xvpp (12 v) t pd(off) 25 latch to xvpp (5 v) t pd(on) 0.6 latch to xvpp (5 v) t pd(off) 8.5 latch to xvpp (3.3 v), t pd(on) 0.6 c l(xvcc) = 0.1 f, latch to xvpp (3.3 v), v i(5v) = 5 v t pd(off) 9 c l(xvcc) = 0.1 f, c l(xvpp) = 0.1 f, latch to xvpp (3.3 v), t pd(on) 1.4 c l(xvpp) = 0.1 f, i o(xvcc) = 0 , i o(xvpp) = 0 latch to xvpp (3.3 v), v i(5v) = 0 v t pd(off) 9 i o(xvcc) = 0 , i o(xvpp) = 0 latch to xvcc (5 v) t pd(on) 0.3 latch to xvcc (5 v) t pd(off) 15 latch to xvcc (3.3 v), t pd(on) 0.2 latch to xvcc (3.3 v), v i(5v) = 5 v t pd(off) 15 latch to xvcc (3.3 v), t pd(on) 0.4 t pd propagation delay ? latch to xvcc (3.3 v), v i(5v) = 0 v t pd(off) 15 ms t pd propagation delay ? latch to xvpp (12 v) t pd(on) 4.5 ms latch to xvpp (12 v) t pd(off) 13 latch to xvpp (5 v) t pd(on) 3.3 latch to xvpp (5 v) t pd(off) 8 latch to xvpp (3.3 v), t pd(on) 3 c l(xvcc) = 150 f, latch to xvpp (3.3 v), v i(5v) = 5 v t pd(off) 9 c l(xvcc) = 150 f, c l(xvpp) = 10 f, latch to xvpp (3.3 v), t pd(on) 3 c l(xvpp) = 10 f, i o(xvcc) = 1 a, i o(xvpp) = 50 ma latch to xvpp (3.3 v), v i(5v) = 0 v t pd(off) 9 i o(xvcc) = 1 a, i o(xvpp) = 50 ma latch to xvcc (5 v) t pd(on) 1 latch to xvcc (5 v) t pd(off) 12 latch to xvcc (3.3 v), t pd(on) 0.6 latch to xvcc (3.3 v), v i(5v) = 5 v t pd(off) 12 latch to xvcc (3.3 v), t pd(on) 1 latch to xvcc (3.3 v), v i(5v) = 0 v t pd(off) 12 ? refer to parameter measurement information ? specified by design: not tested in production. no card inserted, assumes 0.1- f recommended output capacitor (see figure 34).
slvs179d ? march 1999 ? revised june 2000 8 post office box 655303 ? dallas, texas 75265 parameter measurement information 50% latch v dd gnd 10% 90% t pd(on) gnd v o(xvpp) propagation delay (xvpp) 50% latch v dd gnd 10% 90% t pd(on) gnd v o(xvcc) propagation delay (xvcc) 10% 90% t r gnd v o(xvpp) rise/fall time (xvpp) t f 10% 90% t r gnd v o(xvcc) rise/fall time (xvcc) t f 50% v dd gnd 10% 90% t on gnd v o(xvcc) turn on/off time (xvcc) xvpp voltage waveforms load circuits i o(xvpp) xvcc 50% latch v dd gnd 10% 90% t on gnd v o(xvpp) turn on/off time (xvpp) i o(xvcc) t pd(off) t pd(off) t off t off figure 1. test circuits and voltage waveforms
slvs179d ? march 1999 ? revised june 2000 9 post office box 655303 ? dallas, texas 75265 parameter measurement information d10 d9 d8 d7 d6 d5 d4 d3 d2 data latch clock d1 d0 data setup time data hold time latch delay time clock delay time note: data is clocked in on the positive edge of the clock. the positive edge of the latch signal should occur before the next p ositive edge of the clock. for definition of d0 to d10, see the control logic table. figure 2. serial-interface timing for independent xvpp switching when mode = 5 v or 3.3 v d8 d7 d6 d5 d4 d3 d2 d1 d0 data latch clock data setup time data hold time latch delay time clock delay time note: data is clocked in on the positive edge of the clock. the positive edge of the latch signal should occur before the next p ositive edge of the clock. for definition of d0 to d8, see the control logic table. figure 3. serial-interface timing when mode = 0 v or floating table of timing diagrams ? figure short-circuit current response, short applied to powered-on 5-v xvcc switch output 4 short-circuit current response, short applied to powered-on 12-v xvpp switch output 5 oc response with ramped load on 5-v xvcc switch output 6 oc response with ramped load on 12-v xvpp switch output 7 ? timing tests are conducted at free-air temperature, v i(5v) = 5 v, v i(3.3v) = 3.3 v, v i(12v) = 12 v, c l = 0.1 f on each output, stby floating.
slvs179d ? march 1999 ? revised june 2000 10 post office box 655303 ? dallas, texas 75265 parameter measurement information figure 4. short-circuit response, short applied to powered-on 5-v xvcc-switch output 200 400 600 800 1000 t ? time ? s 0 v o(oc) 5 v/div i o(vcc) 5 a/div figure 5. short-circuit response, short applied to powered-on 12-v xvpp-switch output 200 400 600 800 1000 t ? time ? s 0 v o(oc) 5 v/div i o(vpp) 5 a/div figure 6. oc response with ramped load on 5-v xvcc-switch output 10 20 30 40 50 t ? time ? ms 0 v o(oc) 5 v/div i o(vcc) 1 a/div figure 7. oc response with ramped load on 12-v xvpp-switch output 4 8 12 16 20 t ? time ? ms 0 v o(oc) 5 v/div i o(vpp) 0.2 a/div
slvs179d ? march 1999 ? revised june 2000 11 post office box 655303 ? dallas, texas 75265 typical characteristics table of graphs figure t pd(on) turnon propagation delay time, 3.3-v xvcc switch vs load capacitance 8 t pd(off) turnoff propagation delay time, 3.3-v xvcc switch vs load capacitance 9 t pd(on) turnon propagation delay time, 5-v xvcc switch vs load capacitance 10 t pd(off) turnoff propagation delay time, 5-v xvcc switch vs load capacitance 11 t pd(on) turnon propagation delay time, 12-v xvpp switch vs load capacitance 12 t pd(off) turnoff propagation delay time, 12-v xvpp switch vs load capacitance 13 t r rise time, 3.3-v xvcc switch vs load capacitance 14 t f fall time, 3.3-v xvcc switch vs load capacitance 15 t r rise time, 5-v xvcc switch vs load capacitance 16 t f fall time, 5-v xvcc switch vs load capacitance 17 t r rise time, 12-v xvpp switch vs load capacitance 18 t f fall time, 12-v xvpp switch vs load capacitance 19 input current at v o(xvcc) = v o(xvpp) =3.3 v vs junction temperature 20 i i input current at v o(xvcc) = v o(xvpp) =5 v vs junction temperature 21 i i input current at v o(xvcc) = 5 v, v o(xvpp) =12 v vs junction temperature 22 static drain-source on-state resistance, 3.3-v xvcc switch (v i(5v) =0) vs junction temperature 23 r ds(on) static drain-source on-state resistance, 3.3-v xvcc switch vs junction temperature 24 r ds(on) static drain-source on-state resistance, 5-v xvcc switch vs junction temperature 25 static drain-source on-state resistance, 12-v xvpp switch vs junction temperature 26 dc input-to-output voltage (drop), 3.3-v xvcc switch (v i(5v) =0) vs load current 27 v io(xvcc) dc input-to-output voltage (drop), 3.3-v xvcc switch vs load current 28 v io(xvcc) dc input-to-output voltage (drop), 5-v xvcc switch vs load current 29 v io(xvpp) dc input-to-output voltage (drop), 12-v xvpp switch vs load current 30 short-circuit current limit, 3.3-v xvcc switch vs junction temperature 31 i os short-circuit current limit, 5-v xvcc switch vs junction temperature 32 i os short-circuit current limit, 12-v xvpp switch vs junction temperature 33 note: electrical characteristics tests are conducted at v i(5v) = 5 v, v i(3.3v) = 3.3 v, v i(12v) = 12 v, c l = 0.1 f on each output, stby floating (unless otherwise noted on figures).
slvs179d ? march 1999 ? revised june 2000 12 post office box 655303 ? dallas, texas 75265 typical characteristics figure 8 0.2 0.1 1 10 100 ? turn-on propagation delay time ? ms 0.4 0.6 turnon propagation delay time, 3.3-v xvcc switch vs load capacitance 1.4 1000 c l ? load capacitance ? f t pd(on) 0.8 1 1.2 dc load = 1 a t j = 0 c t j = 125 c t j = 85 c t j = 25 c t j = ?40 c figure 9 6 0.1 1 10 100 ? turn-off propagation delay time ? ms turnoff propagation delay time, 3.3-v xvcc switch vs load capacitance 14 1000 c l ? load capacitance ? f t pd(off) 8 10 12 dc load = 1 a t j = 0 c t j = 125 c t j = 85 c t j = 25 c t j = ?40 c figure 10 0.2 0.1 1 10 100 ? turn-on propagation delay time ? ms 0.4 0.6 turnon propagation delay time, 5-v xvcc switch vs load capacitance 1.6 1000 c l ? load capacitance ? f t pd(on) 0.8 1 1.4 dc load = 1 a 1.2 t j = 0 c t j = 125 c t j = 85 c t j = 25 c t j = ?40 c figure 11 6 0.1 1 10 100 ? turn-off propagation delay time ? ms turnoff propagation delay time, 5-v xvcc switch vs load capacitance 14 1000 c l ? load capacitance ? f t pd(off) 8 10 12 dc load = 1 a t j = 0 c t j = 125 c t j = 85 c t j = 25 c t j = ?40 c
slvs179d ? march 1999 ? revised june 2000 13 post office box 655303 ? dallas, texas 75265 typical characteristics figure 12 0 0.1 1 10 100 1 turnon propagation delay time, 12-v xvpp switch vs load capacitance 6 1000 c l ? load capacitance ? f 5 dc load = 50 ma 2 3 4 t j = 25 c t j = 125 c t j = 85 c ? turn-on propagation delay time ? ms t pd(on) t j = 0 c t j = ?40 c figure 13 6 0.1 1 10 100 ? turn-off propagation delay time ? ms 8 turnoff propagation delay time dc, 12-v xvpp switch vs load capacitance 16 1000 c l ? load capacitance ? f t pd(off) 10 12 14 dc load = 50 ma t j = 125 c t j = 85 c t j = 25 c t j = 0 c t j = ?40 c figure 14 0 0.1 1 10 100 ? rise time ? ms 1 1.2 rise time, 3.3-v xvcc switch vs load capacitance 2 1000 c l ? load capacitance ? f t r 1.4 1.6 1.8 dc load = 1 a t j = 0 c t j = 125 c 0.2 0.4 0.6 0.8 t j = 85 c t j = 25 c t j = ?40 c figure 15 0 0.1 1 10 100 ? fall time ? ms 0.5 1.5 fall time, 3.3-v xvcc switch vs load capacitance 3.5 1000 c l ? load capacitance ? f t f 2 2.5 3 dc load = 1 a t j = 0 c t j = 125 c t j = 85 c t j = 25 c 1 t j = ?40 c
slvs179d ? march 1999 ? revised june 2000 14 post office box 655303 ? dallas, texas 75265 typical characteristics figure 16 0 0.1 1 10 100 0.2 0.4 rise time, 5-v xvcc switch vs load capacitance 1.8 1000 c l ? load capacitance ? f 1.2 1.4 1.6 dc load = 1 a 0.6 0.8 1 t j = 85 c t j = 125 c t j = 25 c t j = 0 c ? rise time ? ms t r t j = ?40 c figure 17 0 0.1 1 10 100 0.5 1.5 fall time, 5-v xvcc switch vs load capacitance 4 1000 c l ? load capacitance ? f 2 2.5 3.5 dc load = 1 a 1 3 t j = 0 c t j = 125 c t j = 85 c t j = 25 c ? fall time ? ms t f t j = ?40 c figure 18 0 0.1 1 10 100 .5 1.5 rise time, 12-v xvpp switch vs load capacitance 5 1000 c l ? load capacitance ? f 3.5 4 4.5 dc load = 50 ma 2 2.5 3 1 t j = 85 c t j = 125 c t j = 0 c t j = 25 c ? rise time ? ms t r t j = ?40 c figure 19 0 0.1 1 10 100 2 10 fall time, 12-v xvpp switch vs load capacitance 20 1000 c l ? load capacitance ? f 12 14 18 8 16 6 4 dc load = 50 ma t j = 125 c t j = ?40 c t j = 25 c t j = 85 c ? fall time ? ms t f t j = 0 c
slvs179d ? march 1999 ? revised june 2000 15 post office box 655303 ? dallas, texas 75265 typical characteristics figure 20 0 ?50 50 100 20 30 input current at v i(xvcc) = v i(xvpp) = 3.3 v vs junction temperature 100 150 t j ? junction temperature ? c 70 80 90 40 50 60 10 i i ? input current ? a 0 i i(5v) i i(12v) i i(3.3v) figure 21 ?10 ?50 50 100 0 20 120 150 30 40 60 10 50 input current at v i(xvcc) = v i(xvpp) = 5 v vs junction temperature t j ? junction temperature ? c 70 80 90 110 100 i i ? input current ? a 0 i i(12v) i i(3.3v) i i(5v) figure 22 ?10 ?50 50 100 20 30 input current at v i(xvcc) = 5 v, v i(xvpp) = 12 v vs junction temperature 120 150 t j ? junction temperature ? c 70 80 90 40 50 60 100 110 0 10 i i ? input current ? a 0 i i(12v) i i(3.3v) i i(5v) figure 23 0 ?50 50 100 0.01 0.03 0.09 150 0.02 static drain-source on-state resistance, 3.3-v xvcc switch vs junction temperature t j ? junction temperature ? c 0.04 0.05 0.06 0.08 0.07 ? r ds(on) ? static drain-source on-state resistance ? dc load = 1 a v i(5v) = 0 0
slvs179d ? march 1999 ? revised june 2000 16 post office box 655303 ? dallas, texas 75265 typical characteristics figure 24 0 ?50 50 100 0.01 0.03 0.09 150 0.02 static drain-source on-state resistance, 3.3-v xvcc switch vs junction temperature t j ? junction temperature ? c 0.04 0.05 0.06 0.08 0.07 ? r ds(on) ? static drain-source on-state resistance ? dc load = 1 a 0 figure 25 0 0 50 100 0.01 0.04 0.1 150 0.03 static drain-source on-state resistance, 5-v xvcc switch vs junction temperature t j ? junction temperature ? c 0.05 0.06 0.07 0.09 0.08 0.02 ? r ds(on) ? static drain-source on-state resistance ? dc load = 1 a 0 figure 26 0 ?50 50 100 0.1 0.3 1 150 0.2 static drain-source on-state resistance, 12-v xvpp switch vs junction temperature t j ? junction temperature ? c 0.4 0.5 0.6 0.9 0.7 0.8 ? r ds(on) ? static drain-source on-state resistance ? dc load = 50 ma 0 figure 27 0 0 0.2 0.4 0.6 0.01 0.04 0.1 1 0.03 dc input-to-output voltage (drop), 3.3-v xvcc switch vs load current i l ? load current ? a ? dc input-to-output voltage (drop) ? v v io 0.05 0.06 0.07 0.09 0.08 0.02 0.8 125 c v i(5v) = 0 v 85 c 25 c 0 c ?40 c
slvs179d ? march 1999 ? revised june 2000 17 post office box 655303 ? dallas, texas 75265 typical characteristics figure 28 0 0 0.2 0.4 0.6 0.01 0.04 0.1 1 0.03 dc input-to-output voltage (drop), 3.3-v xvcc switch vs load current i l ? load current ? a dc input-to-output voltage (drop) ? v 0.05 0.06 0.07 0.09 0.08 0.02 0.8 125 c 85 c 25 c 0 c ?40 c figure 29 0 0 0.2 0.4 0.6 0.01 0.04 0.1 1 0.03 dc input-to-output voltage (drop), 5-v xvcc switch vs load current i l ? load current ? a dc input-to-output voltage (drop) ? v 0.05 0.06 0.07 0.09 0.08 0.02 0.8 125 c 85 c 25 c 0 c ?40 c figure 30 0 0 0.01 0.02 0.03 0.06 0.05 dc input-to-output voltage (drop), 12-v xvpp switch vs load current i l ? load current ? a dc input-to-output voltage (drop) ? v 0.01 0.02 0.03 0.05 0.04 0.04 125 c 85 c 25 c 0 c ?40 c figure 31 1.6 0 50 100 1.9 150 short-circuit current limit, 3.3-v xvcc switch vs junction temperature t j ? junction temperature ? c ? short-circuit current limit ? a i os 1.65 1.7 1.75 1.85 1.8 ?50
slvs179d ? march 1999 ? revised june 2000 18 post office box 655303 ? dallas, texas 75265 typical characteristics figure 32 1.6 ?50 50 100 1.9 150 short-circuit current limit, 5-v xvcc switch vs junction temperature t j ? junction temperature ? c 1.65 1.7 1.75 1.85 1.8 ? short-circuit current limit ? a i os 0 figure 33 0.3 ?50 50 100 0.4 150 short-circuit current limit, 12-v xvpp switch vs junction temperature t j ? junction temperature ? c ? short-circuit current limit ? a i os 0.32 0.34 0.38 0.36 0 application information overview pc cards were initially introduced as a means to add eeprom (flash memory) to portable computers with limited onboard memory. the idea of add-in cards quickly took hold; modems, wireless lans, global positioning satellite system (gps), multimedia, and hard-disk versions were soon available. as the number of pc card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. to this end, the pcmcia (personal computer memory card international association), comprising members from leading computer, software, pc card, and semiconductor manufacturers, was established. one key goal was to realize the plug-and-play concept. cards and hosts from different vendors should be compatible or able to communicate with one another transparently. pc card power specification system compatibility also means power compatibility. the most current set of specifications (pc card standard) set forth by the pcmcia committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the pc card connector. this power interface consists of two v cc , two v pp , and four ground terminals. multiple v cc and ground terminals minimize connector terminal and line resistance. the two v pp terminals were originally specified as separate signals, but are commonly tied together in the host to form a single node to minimize voltage losses. card primary power is supplied through the v cc terminals; flash-memory programming and erase voltage is supplied through the v pp terminals.
slvs179d ? march 1999 ? revised june 2000 19 post office box 655303 ? dallas, texas 75265 application information designing for voltage regulation the current pcmcia specification for output voltage regulation, v o(reg) , of the 5-v output is 5% (250 mv). in a typical pc power-system design, the power supply has an output-voltage regulation, v ps(reg) , of 2% (100 mv). also, a voltage drop from the power supply to the pc card will result from resistive losses, v pcb , in the pcb traces and the pcmcia connector. a typical design would limit the total of these resistive losses to less than 1% (50 mv) of the output voltage. therefore, the allowable voltage drop, v ds , for the tps2216 would be the pcmcia voltage regulation less the power supply regulation and less the pcb and connector resistive drops: v ds v o(reg) ?v ps(reg) ?v pcb typically, this would leave 100 mv for the allowable voltage drop across the 5-v switch. the specification for output voltage regulation of the 3.3-v output is 300 mv; so, using the same equation by deducting the voltage drop percentages (2%) for power-supply regulation and pcb resistive loss (1%), the allowable voltage drop for the 3.3-v switch is 200 mv. the voltage drop is the output current multiplied by the switch resistance of the tps2216. therefore, the maxim um output current, i o max, that can be delivered to the pc card in regulation is the allowable voltage drop across the ic, divided by the output-switch resistance. i o max v ds r ds(on) the xvcc outputs can deliver 1 a continuously at 5 v and 3.3 v within regulation over the operating temperature range. the xvpp outputs of the ic can deliver 200 ma continuously. overcurrent and overtemperature protection pc cards are inherently subject to damage that can result from mishandling. host systems require protection against short-circuited cards that could lead to power-supply or pcb trace damage. even systems robust enough to withstand a short circuit would still undergo rapid battery discharge into the damaged pc card, resulting in the rather sudden and unacceptable loss of system power. most hosts include fuses for protection. however, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by the manufacturer. the tps2216 takes a two-pronged approach to overcurrent protection, which is designed to activate if an output is shorted or when an overcurrent condition is present when switches are powered up. first, instead of fuses, sense fets monitor each of the xvcc and xvpp power outputs. unlike sense resistors or polyfuses, these fets do not add to the series resistance of the switch; therefore voltage and power losses are reduced. overcurrent sensing is applied to each output separately. excessive current generates an error signal that limits the output current of only the affected output, preventing damage to the host. each xvcc output overcurrent limits from 1 a to 2.2 a, typically around 1.6 a; the xvpp outputs limit from 250 ma to 500 ma, typically around 375 ma. second, when an overcurrent condition is detected, the tps2216 asserts an active low oc signal that can be monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message. in the event that an overcurrent condition persists, causing the ic to exceed its maximum junction temperature, thermal-protection circuitry activates. this shuts down all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis.
slvs179d ? march 1999 ? revised june 2000 20 post office box 655303 ? dallas, texas 75265 application information 12-v supply not required many pc card switches use the externally supplied 12 v to power gate drive and other chip functions; this requires that power be present at all times. the tps2216 offers considerable power savings by using an internal charge pump to generate the required higher gate drive voltages from the 5-v or 3.3-v power supplies. therefore, the external 12-v supply can be disabled except when needed for flash-memory functions, thereby extending battery lifetime. additional power savings are realized by the ic during shutdown mode, in which quiescent current drops to a maximum of 1 a. 3.3-v low-voltage mode the tps2216 will operate in 3.3-v low-voltage mode when 3.3 v is the only available input voltage (v i(5v) =0, v i(12v) = 0). this feature allows host and pc cards to be operated in low-power 3.3-v-only modes such as sleep modes. note that in this operation mode, the ic will derive its bias current from the 3.3-v input pin and can only provide 3.3 v to the outputs. voltage transitioning requirement pc cards are migrating from 5 v to 3.3 v to minimize power consumption, optimize board space, and increase logic speeds. the tps2216 meets all combinations of power delivery as currently defined in the pcmcia standard. the latest protocol accommodates mixed 3.3-v/5-v systems by first powering the card with 5 v, then polling it to determine its 3.3-v compatibility. the pcmcia specification requires that the capacitors on 3.3-v-compatible cards be discharged to below 0.8 v before applying 3.3-v power. this action ensures that sensitive 3.3-v circuitry is not subjected to any residual 5-v charge and functions as a power reset. pc card specification requires that v cc be discharged within 100 ms. pc card resistance can not be relied on to provide a discharge path for voltages stored on pc card capacitance because of possible high-impedance isolation by power-management schemes. the tps2216 includes discharge transistors on all xvcc and xvpp outputs to meet the specification requirement. shutdown mode in the shutdown mode, which can be controlled by bit d8 of the input serial data word, each of the xvcc and xvpp outputs is forced to a high-impedance state. in this mode, the chip quiescent current is limited to 1 a or less to conserve battery power. standby mode the tps2216 can be put in standby mode by pulling stby low to conserve power during low-power operation. in this mode, all of the power outputs (xvcc and xvpp) will have a nominal current limit of 50 ma. stby has an internal 150-k ? pullup resistor. the output-switch status of the device must be set, allowing the output capacitors to charge, prior to enabling the standby mode. changing the setting of the output switches with the device in standby mode may cause an overcurrent response to be generated. mode the mode pin programs the switches in either tps2216 or tps2206 mode. an internal 150-k ? pulldown resistor is connected to the pin. floating or pulling the mode pin low sets the switches in tps2206 mode; pulling the mode pin high sets the switches in tps2216 mode. in tps2206 mode, xvpp outputs are dependent on xvcc outputs. in tps2216 mode, xvpp is programmed independent of xvcc. refer to tps2216 control-logic tables for more information.
slvs179d ? march 1999 ? revised june 2000 21 post office box 655303 ? dallas, texas 75265 application information power supply considerations the tps2216 has multiple pins for each of its 3.3-v and 5-v power inputs and for the switched xvcc outputs. any individual pin can conduct the rated input or output current. unless all pins are connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and less power. it is recommended that all input and output power pins be paralleled for optimum operation. because the two 12-v pins are not internally connected, they must be tied together externally. to increase the noise immunity of the tps2216, the power-supply inputs should be bypassed with a 1- f electrolytic or tantalum capacitor paralleled by a 0.047- f to 0.1- f ceramic capacitor. it is strongly recommended that the switched outputs be bypassed with a 0.1- f (or larger) ceramic capacitor; doing so improves the immunity of the ic to electrostatic discharge (esd). care should be taken to minimize the inductance of pcb traces between the ic and the load. high switching currents can produce large negative voltage t ransients, which forward biases substrate diodes, resulting in unpredictable performance. similarly, no pin should be taken, or allowed to fall, below ?0.3 v. reset and reset inputs to ensure that cards are in a known state after power brownouts or system initialization, the pc cards should be reset at the same time as the host by applying low impedance paths from xvcc and xvpp terminals to ground. a low-impedance output state allows discharging of residual voltage remaining on pc card filter capacitance, permitting the system (host and pc cards) to be powered up concurrently. the active-high reset or active low reset input will close internal switches s1, s4, s7, and s11 with all other switches left open. the tps2216 remains in the low-impedance output state until the signal is deasserted and further data is clocked in and latched. the input serial data can not be latched during reset mode. reset and reset are provided for direct compatibility with systems that use either an active-low or active-high reset voltage supervisor. the reset pin has an internal 150-k ? pulldown resistor and the reset pin has an internal 150-k ? pullup resistor. the device will be reset automatically when powered up. calculating junction temperature the switch resistance, r ds(on) , is dependent on the junction temperature, t j , of the die. the junction temperature is dependent on both r ds(on) and the current through the switch. to calculate t j , first find r ds(on) from figures 23 through 26, using an initial temperature estimate about 50 c above ambient. then calculate the power dissipation for each switch, using the formula: p d r ds(on) i 2 next, sum the power dissipation of all switches and calculate the junction temperature: t j p d r ja t a where: r ja is the inverse of the derating factor given in the dissipation rating table. compare the calculated junction temperature with the initial temperature estimate. if the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate. logic inputs and outputs the serial interface consists of data, clock, and latch leads. the data is clocked in on the positive edge of the clock (see figures 2 and 3). the 11-bit (d0?d10) serial data word is loaded during the positive edge of the latch signal. the positive edge of the latch signal should occur before the next positive edge of the clock occurs.
slvs179d ? march 1999 ? revised june 2000 22 post office box 655303 ? dallas, texas 75265 application information logic inputs and outputs (continued) the tps2216 serial interfaces are compatible with serial-interface pcmcia controllers and current pcmcia and japan electronic industry development association (jeida) standards. an overcurrent output (oc ) is provided to indicate an overcurrent or overtemperature condition in any of the xvcc and xvpp outputs as previously discussed. tps2216 control logic tps2216 mode (mode pulled high) xvpp avpp control signals output v_avpp bvpp control signals output v_bvpp d8 (shdn ) d0 d1 d9 output v_avpp d8 (shdn ) d4 d5 d10 output v_bvpp 1 0 0 x 0 v 1 0 0 x 0 v 1 0 1 0 3.3 v 1 0 1 0 3.3 v 1 0 1 1 5 v 1 0 1 1 5 v 1 1 0 x 12 v 1 1 0 x 12 v 1 1 1 x hi-z 1 1 1 x hi-z 0 x x x hi-z 0 x x x hi-z xvcc avcc control signals output v_avcc bvcc control signals output v_bvcc d8 (shdn ) d3 d2 output v_avcc d8 (shdn ) d6 d7 output v_bvcc 1 0 0 0 v 1 0 0 0 v 1 0 1 3.3 v 1 0 1 3.3 v 1 1 0 5 v 1 1 0 5 v 1 1 1 0 v 1 1 1 0 v 0 x x hi-z 0 x x hi-z tps2206 mode (mode floating or pulled low) xvpp avpp control signals output v_avpp bvpp control signals output v_bvpp d8 (shdn ) d0 d1 output v_avpp d8 (shdn ) d4 d5 output v_bvpp 1 0 0 0 v 1 0 0 0 v 1 0 1 v_avcc 1 0 1 v_bvcc 1 1 0 12 v 1 1 0 12 v 1 1 1 hi-z 1 1 1 hi-z 0 x x hi-z 0 x x hi-z xvcc avcc control signals output v_avcc bvcc control signals output v_bvcc d8 (shdn ) d3 d2 output v_avcc d8 (shdn ) d6 d7 output v_bvcc 1 0 0 0 v 1 0 0 0 v 1 0 1 3.3 v 1 0 1 3.3 v 1 1 0 5 v 1 1 0 5 v 1 1 1 0 v 1 1 1 0 v 0 x x hi-z 0 x x hi-z
slvs179d ? march 1999 ? revised june 2000 23 post office box 655303 ? dallas, texas 75265 application information esd protections (see figure 34) all tps2216 inputs and outputs incorporate esd-protection circuitry designed to withstand a 2-kv human-body-model discharge as defined in mil-std-883c, method 3015. the xvcc and xvpp outputs can be exposed to potentially higher discharges from the external environment through the pc card connector. bypassing the outputs with 0.1- f capacitors protects the devices from discharges up to 10 kv. ? maximum recommended output capacitance for xvcc is 220 f and for xvpp is 10 f without oc glitch when switches are powered on. tps2216 v cc bvpp bvcc bvcc bvcc avpp avcc avcc avcc reset latch clock data oc reset v cc 0.1 f ? 0.1 f ? v pp1 v pp2 pc card connector a v cc v cc 0.1 f ? 0.1 f ? v pp1 v pp2 pc card connector b data clock latch gpi/o controller from pci or system rst 12v 3.3v 5v 12v 3.3v 5v 12v 3.3v 3.3v 5v 5v mode stby 0.1 f 33 f 0.1 f 33 f 0.1 f 10 f figure 34. detailed interconnections and capacitor recommendations
slvs179d ? march 1999 ? revised june 2000 24 post office box 655303 ? dallas, texas 75265 application information 12-v flash memory supply the tps6734 is a fixed 12-v output boost converter capable of delivering 120 ma from inputs as low as 2.7 v. the device is pin-for-pin compatible with the max734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. as shown in figure 35, the only external components required are: an inductor, a schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. the entire converter occupies less than 0.7 in 2 of pcb space when implemented with surface-mount components. an enable input is provided to shut the converter down and reduce the supply current to 3 a when 12 v is not needed. the tps6734 is a 170-khz current-mode pwm (pulse-width modulation) controller with an n-channel mosfet power switch. gate drive for the switch is derived from the 12-v output after start-up to minimize the die area needed to realize the 0.7- ? mosfet and improve efficiency at input voltages below 5 v. soft start is accomplished with the addition of one small capacitor. a 1.22-v reference (pin 2) is brought out for external use. for additional information, see the tps6734 data sheet (slvs127). note a: the enable terminal can be tied to a general-purpose i/o terminal on the pcmcia controller or tied high. tps2216 bvpp bvcc bvcc bvcc avpp avcc avcc avcc reset latch clock data oc reset 3.3 v 5 v 12v 3.3v 5v 12v 3.3v 3.3v 5v 5v mode stby 0.1 f 0.1 f 33 f 0.1 f 33 f en ref ss comp tps6734 vcc fb out gnd 1 2 3 4 l1 18 h 8 7 6 5 r1 10 k ? enable (see note a) c1 33 f 20v c2 0.01 f 12 v d1 33 f, 20 v c4 0.001 f 3.3v or 5v + c1 + figure 35. tps2216 with tps6734 12-v, 120-ma supply
package option addendum www.ti.com 10-aug-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS2216DAP active htssop dap 32 46 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tps2216 TPS2216DAPr active htssop dap 32 tbd call ti call ti tps2216 tps2216db active ssop db 30 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tps2216 tps2216dbg4 active ssop db 30 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tps2216 tps2216dbr active ssop db 30 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tps2216 tps2216dbrg4 active ssop db 30 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tps2216 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 10-aug-2016 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps2216dbr ssop db 30 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 q1 package materials information www.ti.com 10-aug-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps2216dbr ssop db 30 2000 367.0 367.0 38.0 package materials information www.ti.com 10-aug-2016 pack materials-page 2

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
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